Method of Improving Processing Efficiency Decision Making Within a Computer System

ABSTRACT

The method disclosed herein includes preprocessing large amounts of input data into a smaller input data sets based on first predetermined associations, sorting the smaller input data sets into groups based on second predetermined associations, filtering grouped data based on upper and lower thresholds, updating a hierarchical processing decision tree within a processor of a computing system, processing data based on the updated hierarchical processing decision tree, and recursively restarting the preprocessing of the large amounts of input data to dynamically update the hierarchical processing decision tree within a user device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. patent application Ser. No. 15/862,631 filed 5 Jan. 2018, which is incorporated by reference herein in its entirety.

BACKGROUND Technical Field

This invention relates to preprocessing large data sets into smaller data sets and programming processor functionality based on the smaller data sets.

Summary

The method disclosed herein includes preprocessing large amounts of input data into a smaller input data sets based on first predetermined associations, sorting the smaller input data sets into groups based on second predetermined associations, filtering grouped data based on upper and lower thresholds, updating a hierarchical processing decision tree within a processor of a computing system, processing data based on the updated hierarchical processing decision tree, and recursively restarting the preprocessing of the large amounts of input data to dynamically update the hierarchical processing decision tree

A method of improving processing efficiency of decision making within a computing system includes one or more processors with non-transitory memory programmed to: preprocess a plurality of data inputs at time T₁ to time T_(n), create a reduced plurality of virtual data inputs based on first predetermined associations of the plurality of data inputs, sort the virtual data inputs into groups based on second predetermined associations within the reduced plurality of virtual data inputs, assign first conditionally weighted variables to each of the groups based at least in part on the second predetermined associations; assign second conditionally weighted variables to each virtual data input of each group based at least in part on a relation to the first conditionally weighted variables of each group, create upper and lower threshold limits for each group related to the first conditionally weighted variables or the second conditionally weighted variables, eliminate all virtual data inputs that fall outside of the upper or the lower threshold limits within each group, update a hierarchical processing decision tree based on the virtual data inputs not eliminated within the groups, start hierarchical processing within the computing system based on the updated hierarchical processing decision tree, and recursively restart the preprocessing of the plurality of data inputs. The plurality of data inputs may be transmitted to the computing system from 10 or more servers in different physical locations. The virtual data inputs may be stored in a database server. The updated hierarchical processing decision tree may be stored in one or more of a user device, a database server, and ASIC (application specific integrated circuit), an FPGA (field programmable gate array), or an FPBGA (fine-pitch ball grid array). The updated hierarchical processing decision tree may be part of a processing blockchain or a parallel processing filter. The plurality of data inputs may be transmitted to the computing system from one or more imaging sensors. The plurality of data inputs may be transmitted to the computing system from one or more biological sensors. The plurality of data inputs may be transmitted to the computing system from one or more Internet devices. The hierarchical processing may produce a real-time bi-stable decision based on a large data set of the plurality of data inputs. The imaging sensors may be used to gather data related to one or more of: fraud, biological identity, pharmaceutical drug creation, pharmaceutical drug testing, positional tracking, location tracking, navigation, electromagnetic imaging, medical procedures, and object detection. Time Ti to time Tn may represent one or more of sets of time in: milliseconds, seconds, minutes, hours, days, weeks, and/or years. The first predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The second predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The first conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group. The second conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group. The real-time bi-stable decision may cause one or more of the following: unlocking of a secure entry, identity authentication, yes/no decisions, purchase transaction decisions, sell transaction decisions, biological identity decisions, fraud decisions, or providing of a bi-stable output. The updated hierarchical processing decision tree may cause at least one function of the one or more processors to be updated. The updated hierarchical processing decision tree (gate-level-logic) may change a physical processing feature of the at least one or more processors. The updated hierarchical processing decision tree (gate level-logic) may create a new processor function to be added to the at least one or more processors. The updated hierarchical processing decision tree may cause the at least one or more processors to update a filtering algorithm within the at least one or more processors.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through use of the accompanying drawings, in which:

FIG. 1 shows a flow diagram in accordance with an embodiment of the invention.

FIG. 2 shows a flow diagram in accordance with an embodiment of the invention;

FIG. 3 shows a flow diagram in accordance with an embodiment of the invention;

FIG. 4 shows a flow diagram in accordance with an embodiment of the invention; and

FIG. 5 shows a flow diagram in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the invention, as represented in the Figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of certain examples of presently contemplated embodiments in accordance with the invention. The presently described embodiments will be best understood by reference to the drawings.

FIG. 1 shows a flow diagram 100 in accordance with an embodiment of the invention. Data 102 may be obtained from the Internet, Internet sensors, Ethernet sensors, wireless sensors, mesh network devices, local network devices, wide area network devices, stored database records, Internet of Things (IoT) sensors, or from dynamic database records. Data 102 may be defined as networked data, stored data, or sensor data. Data 102 may be received by one or more preprocessors 106 and time and date stamped with intervals Tt to Tn. Intervals Ti to Tn may represent actual collection times of data or may represent recursively restarted preprocessing cycles depending on the specific embodiment. Intervals Tt to Tn may be used to form one or more associations between data from the same data sources taken at different times and/or may represent data from various different data sources at similar and/or different times depending on the specific embodiment. Preprocessors 106 may be networked processors, a single device processor, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGA), or parallel processors used to preprocess data 102 into smaller virtual input sets or smaller data sets. Preprocessors 106 may receive indirect user instructions in the form of programming 114 or direct user instructions by way of input 110. User input 110 may represent programming parameters used to preprocess the data into smaller virtual data input sets 106. Such programming parameters may be used to define first predetermined associations. First predetermined associations may include associations between data within data set 102. The associations may allow filtering, truncating, sorting, extracting, defining, or refining of smaller sets of data from larger data set 102. Examples of first predetermined associations may include associations of one or more of: positional data, timing of collected data, differences of data collected at different times, deltas between similar data, deltas between different data, deltas between the same data sources taken at different times, event data, location data, frequency data, color data, shape data, temperature data, size data, time of day data, date data, amount data, name data, type data, class data, logic data, Boolean logic data, price data, market data, company data, employee data, asset data, and/or product data. The first predetermined association allows data 102 to be preprocessed into a smaller virtual data input set 106. The smaller virtual input data set may then be sorted, reduced, simplified, and/or organized based on second predetermined associations. Second predetermined associations 108 may include one or more of: positional data, timing of collected data, differences of data collected at different times, deltas between similar data, deltas between different data, deltas between the same data sources taken at different times, event data, location data, frequency data, color data, shape data, temperature data, size data, time of day data, date data, amount data, name data, type data, class data, logic data, Boolean logic data, price data, market data, company data, employee data, asset data, and/or product data. First and second conditionally weighted variables may include user defined or program defined associations which define extreme conditions such as greatest separation, least separation, greatest deviation, least deviation, no deviation, and other conditions which assist in the formation of gate-level logic programming. Upper and lower threshold limits may allow the data to be further filtered, sorted, and prepared to be used as an input to a compiler program. The sorted virtual input data 108 may then be used as in input to form simplified logic conditions allowing for dynamically compiled and programmed gate-level-logic within FPGAs, ASICs, processors, one or more programmable logic blocks, filters, and/or memory locations 116. Dynamic on-the-fly programming may be accomplished using re-configurable or partially re-configurable FPGAs, ASICs, or memory locations of traditional processors. Verilog, VHDL, gate-level-logic, C, C++, Java or other languages may be used to program the re-configurable FPGAs, ASICs, or memory locations of traditional processors. Sorted virtual data inputs 108 may be used as data inputs to a compiler program that produces the dynamic programming for the re-configurable FPGAs, ASICs, or memory locations of traditional processors. An input or question 112 may then be processed or filtered through dynamic filters or logic gates/states to produce a fast bi-stable logic output 118. Output 118 may be used to control devices, make decisions, purchase merchandise, authenticate identity, provide access control, and other uses as described in relation to FIGS. 3-5 . Computing system 104 may include a combination of cloud computing, local device computing, remote device computing, local area computing, wide area computing, Internet computing, intranet computing and/or wireless network computing. The first predetermined associations and the second predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The first conditionally weighted variables and the second conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group. Computing system 104 may include servers, database servers, smart phones, computers, notebooks, tablets, cameras, sensors, optical sensors, smart locks, smart devices, alarms, appliances, and other network capable devices.

FIG. 2 shows a flow diagram 200 in accordance with an embodiment of the invention. Ten or more data sources 202 may be obtained from the Internet, Internet sensors, Ethernet sensors, wireless sensors, mesh network devices, local network devices, wide area network devices, stored database records, Internet of Things (IoT) sensors, or from dynamic database records. Data 202 may be defined as networked data, stored data, or sensor data. Data 202 may be received by one or more preprocessors 206 and time and date stamped with intervals Ti to Tn. Intervals Ti to Tn may represent actual collection times of data or may represent recursively restarted preprocessing cycles depending on the specific embodiment. Intervals Ti to Tn may be used to form one or more associations between data from the same data sources taken at different times and/or may represent data from various different data sources at similar and/or different times depending on the specific embodiment. Preprocessors 206 may be networked processors, a single device processor, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGA), or parallel processors used to preprocess data 202 into smaller virtual input sets or smaller data sets. Preprocessors 206 may receive indirect user instructions in the form of programming 214 or direct user instructions by way of input 210. User input 210 may represent programming parameters used to preprocess the data into smaller virtual data input sets 206. Such programming parameters may be used to define first predetermined associations. First predetermined associations may include associations between data within data set 202. The associations may allow filtering, truncating, sorting, extracting, defining, or refining of smaller sets of data from larger data set 202. Examples of first predetermined associations may include associations of one or more of: positional data, timing of collected data, differences of data collected at different times, deltas between similar data, deltas between different data, deltas between the same data sources taken at different times, event data, location data, frequency data, color data, shape data, temperature data, size data, time of day data, date data, amount data, name data, type data, class data, logic data, Boolean logic data, price data, market data, company data, employee data, asset data, and/or product data. The first predetermined association allows data 202 to be preprocessed into a smaller virtual data input set 206. The smaller virtual input data set may then be sorted, reduced, simplified, and/or organized based on second predetermined associations. Second predetermined associations 208 may include one or more of: positional data, timing of collected data, differences of data collected at different times, deltas between similar data, deltas between different data, deltas between the same data sources taken at different times, event data, location data, frequency data, color data, shape data, temperature data, size data, time of day data, date data, amount data, name data, type data, class data, logic data, Boolean logic data, price data, market data, company data, employee data, asset data, and/or product data. First and second conditionally weighted variables may include user defined or program defined associations which define extreme conditions such as greatest separation, least separation, greatest deviation, least deviation, no deviation, and other conditions which assist in the formation of gate-level logic programming. Upper and lower threshold limits may allow the data to be further filtered, sorted, and prepared to be used as an input to a compiler program. The sorted virtual input data 208 may then be used as in input to form simplified logic conditions allowing for dynamically compiled and programmed gate-level logic within FPGAs, ASICs, processors, one or more programmable logic blocks, filters, and/or memory locations 216. Dynamic on-the-fly programming may be accomplished using reconfigurable or partially re-configurable FPGAs, ASICs, or memory locations of traditional processors. Yerilog, VHDL, gate-level-logic, C, C++, Java or other languages may be used to program the re-configurable FPGAs, ASICs, or memory locations of traditional processors. Sorted virtual data inputs 208 may be used as data inputs to a compiler program that produces the dynamic programming for the re-configurable FPGAs, ASICs, or memory locations of traditional processors. An input or question 212 may then be processed or filtered through dynamic filters or logic gates/states to produce a fast bi-stable logic output 218. Output 218 may be used to control devices, make decisions, purchase merchandise, authenticate identity, provide access control, and other uses as described in relation to FIGS. 3-5 . Computing system 204 may include a combination of cloud computing, local device computing, remote device computing, local area computing, wide area computing, Internet computing, intranet computing and/or wireless network computing. The first predetermined associations and the second predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The first conditionally weighted variables and the second conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group. Computing system 204 may include servers, database servers, smart phones, computers, notebooks, tablets, cameras, sensors, optical sensors, smart locks, smart devices, alarms, appliances, and other network capable devices.

FIG. 3 shows a flow diagram 300 in accordance with an embodiment of the invention. In an embodiment, identification data may be stored in the cloud 302. Identification information may include fingerprints, retinal eye scan data, palm print data, DNA data, or any other large data biometric identifier. Cloud processing 302 may reduce a retinal eye scan from 30 Megabytes to 30 Kilobytes keeping data needed to authenticate an individual, a biometric key. This key may have been made by cloud processing of the large data file using first and second predetermined (association) identifiers such as exact pixel positioning, pixel shape, and/or pixel intensity of a stored retinal eye scan. The virtual input data set of 30 Kilobytes may compiled into gate-level-logic and be wirelessly and dynamically loaded in an inexpensive reconfigurable FPGA chip of an retinal eye access point. The user requesting entrance may then have his eye quickly scanned and the data filtered through the access point FPGA resulting in a quick bi-stable logic condition allowing access or denying access. The first predetermined associations and the second predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The first conditionally weighted variables and the second conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group.

FIG. 4 shows a flow diagram 400 in accordance with an embodiment of the invention. In another embodiment, sensor data 406 may be derived from imaging sensors and may be stored in the cloud 402 for the purpose of detecting fraud, biological identity, pharmaceutical drug creation, pharmaceutical drug testing, positional tracking, location tracking, navigation, electromagnetic imaging, medical procedures, and object detection. Cloud processing 402 may reduce large image sensor data to very small amounts only keeping data needed to perform a very specific logic function. This specific logic function may have been obtained by cloud processing of the large data files using first and second predetermined association and first and second conditionally weighted variables. First and second predetermined association and first and second conditionally weighted variables may include one or more of: pixel positioning, pixel shape, pixel intensity, positional data, timing of collected data, differences of data collected at different times, deltas between similar data, deltas between different data, deltas between the same data sources taken at different times, event data, location data, frequency data, color data, shape data, temperature data, size data, time of day data, date data, amount data, name data, type data, class data, logic data, Boolean logic data, price data, market data, company data, employee data, asset data, and/or product data. A small virtual input data set may be compiled into gate level-logic and be wirelessly and dynamically loaded in an inexpensive re-configurable FPGA chip of one or more devices. The one or more devices may produce a fast bi-stable logic output derived from a large data set. The first predetermined associations and the second predetermined associations may be one or more of: statistical associations of the plurality of data inputs, industry associations of the plurality of data inputs, historically learned associations of the plurality of data inputs, or user selected associations of the plurality of data inputs. The first conditionally weighted variables and the second conditionally weighted variables may be assigned based on one or more of: changes in relation to time between the groups, changes in relation to time between the virtual data inputs within the group, a predicted rate of change of one or more of the groups, and/or a predicted rate of change of one or more of the virtual data inputs within each group.

FIG. 5 shows a flow diagram 500 in accordance with an embodiment of the invention. In another embodiment, a user device 508 selects first and second predetermined associations related to a specific home he wants to buy. The first predetermined association is the housing market condition in general and the second predetermined association is the exact address of the house. The first and second conditionally weighted variables are chosen to be value thresholds, historical rates of change of the housing market sector, and the specific home real-time value change over minutes. Additional user settings may include: predicted future value, additional data inputs, timing or refreshing of the preprocessing. To start preprocessing, data is received into the cloud based processing 502 from input sensors and input devices. Devices 506 may include Internet new reports, historical database records, smart phones, networks, or other information channels such as television, radio, media outlets, etc. The user 508 sets processing parameters in the cloud based processing and the cloud generates compiled gate-level-logic that is recursively downloaded into his watch 504 and updated every 1 minute. The user can push a button on his watch 504 and find out if the house meets his predefined conditions for purchase in near real-time. An automated purchase action may be implemented by user server settings. Device 504 could be any electronic device such as a smart phone, watch, tablet, computer, vehicle computer, etc. Device 504 and device 508 may be the same electronic device. Similar buy/sell financial transactions could also be implemented by the disclosed systems, devices, and methods.

The apparatus and methods disclosed herein may be embodied in other specific forms without departing from their spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. 

1. (canceled)
 2. (canceled)
 3. A method of improving processing efficiency of decision making within a computing system comprising: one or more processors with non-transitory memory programmed to: preprocess a plurality of data inputs at time T1 to time Tn; create a reduced plurality of virtual data inputs based on first predetermined associations of the plurality of data inputs; sort the virtual data inputs into groups based on second predetermined associations within the reduced plurality of virtual data inputs; assign first conditionally weighted variables to each of the groups based at least in part on the second predetermined associations; assign second conditionally weighted variables to each virtual data input of each group based at least in part on a relation to the first conditionally weighted variables of each group; create upper and lower threshold limits for each group related to the first conditionally weighted variables or the second conditionally weighted variables; update a hierarchical processing decision tree based on the reduced plurality of virtual data inputs; start hierarchical processing within the computing system based on the updated hierarchical processing decision tree; recursively restart the preprocessing of the plurality of data inputs; wherein the hierarchical processing produces a real-time bi-stable decision based on the plurality of data inputs; and and wherein the real-time bi-stable decision causes one or more of the following: unlocking of a secure entry, identity authentication, yes/no decisions, purchase transaction decisions, sell transaction decisions, biological identity decisions, fraud decisions, or providing of a bi-stable output.
 4. The invention of claim 3, wherein the one or more processors is further programmed to eliminate all virtual data inputs that fall outside of the upper or the lower threshold limits within each group. 